Non-volatile memory (NVM) systems include arrays of NVM cells that are programmed using program bias voltages applied to program nodes. NVM systems can also be embedded within other integrated circuits, such as for example, microcontrollers and/or microprocessors. Many NVM systems, including embedded NVM systems, utilize smart program biasing and erase biasing where program/erase bias voltages are ramped, stepped and/or pulsed from a low voltage bias level to a higher voltage bias level in order to minimize stress to cells within the NVM array.
FIG. 1 (Prior Art) is a block diagram of an embodiment 100 for regulating a program voltage (VPRG) 108 that is used to program cells within an NVM array. Voltage pump circuitry 102 receives an enable signal (EN) 104, receives an oscillation input signal (OSC) 106, and generates a regulated program voltage (VPRG) 108 that is applied to program drivers 110 for an NVM array. The regulation of the program voltage (VPRG) 108 is provided through a voltage feedback signal (VFB) 116 that is received by the voltage pump circuitry 102. The voltage feedback signal (VFB) 116 is generated by a comparator 114 that compares the generated program voltage (VPRG) 108 to a reference voltage (VREF) 112. In operation, the voltage pump circuitry 102 uses the voltage feedback signal (VFB) 116 to keep the program voltage (VPRG) 108 at a selected voltage level as set by the reference voltage (VREF) 112. The reference voltage (VREF) 112 is changed if different voltage levels are desired. The program voltage (VPRG) 108, however, can be affected by IR (current-resistance) losses when used to feed program voltage drivers through relatively long distribution lines.
FIG. 2 (Prior Art) is a block diagram of an embodiment 200 for an NVM cell array 206 that receives generated program voltages. For embodiment 200, the NVM cell array 206 includes eight sectors (e.g., Sector0, Sector1 . . . Sector7) of split-gate thin film storage (SGTFS) NVM cells, which include control gates, select gates, sources, and drains. Each sector has a control gate driver (CGDrv) that applies a high voltage (HV) output signal from the program voltage generation circuitry 202 to cells within the sector that have been selected for programming. A distribution line 208 feeds the HV output signal to control gate drivers. Each sector also has a source gate driver (SRCDrv) that applies a medium voltage (MV) output signal (e.g., the program voltage (VPRG) in FIG. 1) from the program voltage generation circuitry 202 to cells within the sector that have been selected for programming. A distribution line 210 feeds the MV output signal to the source gate drivers. As the source gate nodes are relatively low impedance nodes, a high current will travel along the distribution line 210. Due to the different distances and potentially long distance 204 (e.g., 2.2 millimeters) that this current will travel along distribution line 210, for example to Sector7, different and potentially large IR (current-resistance) voltage drops will occur. As such, the voltages actually applied to the NVM cells through the source drivers can be less than the desired program voltage level. As the control gate nodes are relatively high impedance nodes, the IR voltage drop along the distribution line 208 is not significant.
FIG. 3 (Prior Art) is a block diagram of an embodiment 300 for variations in program pulse voltages due to IR voltage losses experienced in distributing program voltages to source drivers within an NVM array. The x-axis 304 represents time, and the y-axis 302 represents pulse voltage. For the embodiment 300, three program pulses are shown. Pulse voltage levels 306, 308, and 310 represent desired pulse voltage levels for pulses that ramp to 4.0 volts, 5.0 volts, and 6.0 volts, respectively. Actual voltage pulses 312, 314, and 316 do not reach the desired voltage levels due to IR voltage losses. For example, an IR voltage loss of about 0.1 volts can be experienced when the program voltage (VPRG) 108 of FIG. 1 is used to drive source nodes for 72 cells at 1 milli-Amp (mA) through program voltage drivers located at the end of a voltage distribution line that is 2.2 millimeters (mm). It is noted that the sheet resistance for the distribution line, the sector selected, and the current level will affect this IR loss. It is also noted that the current level is determined by the number of cells selected for programming within the NVM array.